The present embodiments relate to domino logic technology, and are more particularly directed to domino logic circuits, systems, and methods with precharge control based on the completion of evaluation by the subsequent domino logic stage.
In many modern circuit applications, it is often desirable to increase the speed of operation of the circuit application. For example, in microprocessor design the circuits which make up speed-limiting portions or affect the speed of the microprocessor are constantly scrutinized and re-designed to increase the overall microprocessor speed. Increased speed increases performance and, therefore, permits more detailed and sophisticated processing capabilities in a shorter amount of time.
To increase the speed of microprocessors, as well as other circuits where speed is important, domino logic transistor circuits are currently used because they often provide increased speed as compared to static logic transistor circuits. A domino logic circuit is characterized by operating in two phases. First, a precharge node is set to a first potential during a precharge phase. Second, during an evaluate phase, if the logic condition represented by the circuit is satisfied, the precharged node is discharged, thereby changing the logic output of the circuit. In other words, at the conclusion of the precharge phase, the precharged node causes a first logic state to be output by the domino logic circuit. Thereafter, if the precharged node is discharged during the evaluate phase, the output of the domino logic circuit represents a second logic state differing from the first logic state. Moreover, the act of discharging to change states, when accomplished using one or more n-channel transistors to gate the transition from precharge to discharge, represents a speed increase over the prior operation of static circuits which in one instance accomplished a transition with a network of n-channel transistors while in another instance accomplished the opposite transition with a network of p-channel transistors.
One specific example of domino logic transistor circuits is known as a hold-time latch. The hold time latch generally follows the principles set forth above as characteristic of domino logic circuits, but as detailed later also takes advantage of a delay in precharging the latch. More specifically, the hold-time latch is connected to output a data signal to a subsequent domino logic stage, where the subsequent domino stage evaluates out of phase with respect to the hold-time latch. Thus, when the hold-time latch completes its evaluate phase, the subsequent stage then performs its evaluate phase based on the data from the hold-time latch. Note, however, that at the same time the subsequent stage begins its evaluate phase, the hold-time latch beings its precharge phase. By design, however, there is a slight delay of time from this point where, even though the control signals have changed to cause the beginning of the precharge phase of the hold-time latch, the output of the hold-time latch from its preceding evaluate phase remains valid. It is during this time, known as the hold time, that the subsequent stage is typically able to trigger (i.e., evaluate) based on the valid data from the hold-time latch. Consequently, data may propagate through this as well as similar connections without the need for complicated additional latching circuitry.
While the above approaches are representative of the art for advancing circuit operational speed, they provide various limitations or drawbacks. For example, the length of the hold-time latch must be long enough to allow the subsequent stage to trigger. Thus, there is effectively a "race" between the hold-time latch and its subsequent stage, whereby the subsequent stage races to trigger based on the data from the hold time while the hold-time latch races to begin its next precharge operation. Note that when this next precharge operation reaches a certain point, it eliminates the valid data and, therefore, ends the hold time. Thus, if the hold-time latch reaches this critical precharge point before the subsequent stage is able to trigger, the circuit fails its purpose and the integrity of the data is lost. The inventor of the present embodiments has recognized these above considerations and below sets forth various embodiments which provide circuit speed while reducing concern over data integrity in domino logic as compared to the current state of the art.